National Instruments cRIO-9049 CompactRIO Controller

The cRIO-9049 (Part Number: 785618-01) is a CompactRIO Controller. This model uses the Single-Cycle Timed Loop as it completes a While Loop. The user can utilize most VIs and capacities accessible when they focus on a FPGA gadget in a Single-Cycle Timed Loop. A few VIs and capacities cannot execute in a solitary FPGA clock cycle. LabVIEW restores a code age or aggregate time mistake if the sub diagram cannot execute in a solitary cycle. The Single-Cycle Timed Loop is like a checked procedure in VHDL. The move registers, advanced yield capacities, and markers are registers empowered by the contingent terminal in the Single-Cycle Timed Loop. All other LabVIEW code in the Single-Cycle Timed Loop is combinatorial rationale on the FPGA gadget. Contributions to the combinatorial rationale are outputs from segments, such as computerized input capacities, controls, or left move registers.

The user can utilize computerized FPGA Device I/O capacities like the Digital Input work, in the Single-Cycle Timed Loop if the FPGA gadget bolsters utilizing the advanced FPGA Device I/O works in the Single-Cycle Timed Loop. The user can allude to the equipment documentation to decide if the gadget underpins advanced FPGA Device I/O works in the Single-Cycle Timed Loop.

The FPGA Module incorporates capacities for performing fundamental I/O. Be that as it may, the user may have applications that require further developed or custom I/O usefulness. Utilize the FPGA Device I/O works as building squares to make modified I/O usefulness, which includes activating and counters.