E2930B

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Keysight/Agilent E2930B, Bus Validation, USB 2.0, 16-Level Trigger Sequencing, DDR Exerciser and Protocol Analyzer for PCI-X 1.0 and 2.0

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Keysight Agilent HP - Protocol Analyzers and Exercisers - E2930B
Keysight Agilent HP - Protocol Analyzers and Exercisers - E2930B - Wiring
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Keysight/Agilent E2930B DDR Exerciser and Protocol Analyzer for PCI-X 1.0 and 2.0

The Keysight E2930B is a short-form PCI card used to debug, validate, and stress test PCI-X 1.0 & 2.0-based designs (i.e., servers, motherboards, chipsets, RAID controllers, and network interface cards). It performs the function of a bus validation tool by combining a real-time protocol checker, a full-featured exerciser, and a deep-state logic analyzer into one card.

The Keysight E2930B has the capability to operate at speeds up to 266 MT/s DDR. There are two options for controlling the Keysight E2930B; engineers may control it directly from the system being tested using the PCI-X 2.0 bus, or they may connect it to an external host using the built-in USB 2.0 interface for fast data transfer. Control software is available through several interfaces, including a graphical user interface, a C-language API, and a TCL scripting interface, allowing for either manual interaction or automated compliance testing and/or corner-case testing.

The exerciser portion of the Keysight E2930B includes requester and completer functions, which are fully programmable; 4MB of memory for data storage, organized as 512k x 64 bit; the ability to generate data in real time; and hardware-based data comparisons for bidirectional integrity checks. The PCI-X protocol rules engine included with the Keysight E2930B is able to monitor and enforce 64 spec-derived rules in real time, flagging violations, and will allow engineers to capture states from the analyzer or other external logic analyzers. The analyzer is capable of capturing up to 4 million samples of all 64-bit address/data signals present on the PCI-X bus along with bus state decoding and any external triggers. In addition, engineers have complete control over how these samples are stored.

Additionally, there is a 16-level trigger sequencer that allows engineers to identify very specific protocol events using 11 pattern terms. In order to perform exhaustive validation of their systems, designers and engineers can utilize the patented Protocol Permutator and Randomizer technology to automatically generate thousands of deterministic transaction permutations every second. These permutations help identify potential corner cases associated with data integrity. Engineers who need additional tools can purchase an optional System Validation Pack containing pre-written compliance tests. As a final note, multiple Keysight E2930B's can be synchronized together in order to perform testing across different buses or systems utilizing external trigger cable connections.

E2930B Technical Specifications
ModelE2930B
Part TypePCI-X Exerciser & Protocol Analyzer
Bus Standard SupportPCI-X 1.0 and 2.0 (Mode 1 & Mode 2)
Max Data RateUp to 266 MT/s DDR
Bus Width64-bit data and addressing
Operating Frequency66 / 100 / 133 MHz
Exerciser Memory4 MB (512K × 64-bit)
Trace Memory Depth4M samples state capture
Protocol Checking64 concurrent PCI-X rule checks
Control InterfacesPCI-X system bus or USB 2.0

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